| 摘要 |
PROBLEM TO BE SOLVED: To suppress latency increase of other access to a minimum without reducing priorities of DMA transfer of a Y signal and a C signal. SOLUTION: A data processing apparatus includes: an image data input module (32) capable of separating the Y signal and the C signal from a video signal; a DMA controller capable of performing DMA transfer of the Y signal and C signal to a predetermined semiconductor memory; and a bus capable of exchanging signals between the image data input module and the DMA controller. Then, the image data input module is provided with a DMA transfer control circuit (323) for issuing, after waiting for the lapse of just predetermined bus cycles on the bus from the DMA transfer of either one of the Y signal or the C signal, the DMA transfer request of the other signal to the DMA controller, thereby suppressing the latency increase of other access to the minimum without reducing priorities of DMA transfer of the Y signal and the C signal. COPYRIGHT: (C)2009,JPO&INPIT
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