| 发明名称 |
DESIGNING INTEGRATED CIRCUITS FOR YIELD |
| 摘要 |
Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found.
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| 申请公布号 |
US2009144671(A1) |
申请公布日期 |
2009.06.04 |
| 申请号 |
US20070947737 |
申请日期 |
2007.11.29 |
| 申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
LIU HONGZHOU;CLARK GLEN;NEUREUTER LORENZ;ZHANG HUI |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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