| 摘要 |
<P>PROBLEM TO BE SOLVED: To laminate in three dimensions with ease and with fewer number of processes even in a semiconductor chip having a different outline dimension or in a semiconductor chip in which a wiring is not formed preliminarily on a side surface. <P>SOLUTION: An adhesive agent containing a conductive filler is supplied on a first surface on which an electrode pad 2 is formed and on all over side surface of a laminated semiconductor chip 1, and rewirings 4a and 4b which electrically connect between predetermined electrode pads 2 through the first surface and the side surface are formed. This leads to that an electrically connected semiconductor chip lamination module can be formed with ease by forming the rewiring with the same material even when laminating the semiconductor chip 1 in which an electrode pad for connecting between the semiconductor chips 1 laminated on the side surface is not formed, or even when laminating the semiconductor chips having a different outline dimension. <P>COPYRIGHT: (C)2009,JPO&INPIT |
