发明名称 IMAGE PROCESSING APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of reducing an amount of pixel value transfer in comparison with SIMD construction and avoiding a problem of an RCSA construction (an increase in the number of cycles attributed to H. 264 block division). <P>SOLUTION: The image processing apparatus includes an array in which a plurality of arithmetic elements PE are disposed in a matrix shape. The array is divided into a plurality of sub-blocks SBSA each of which includes the prescribed number of arithmetic elements PE. Each of the plurality of sub-blocks SBSA has multiplexers 10A and 11A capable of selecting whether a self sub-block and an adjacent sub-block adjacent to the self sub-block are connected. By switching setting of the multiplexers 10A and 11A in accordance with size of an image to be processed, one or more blocks including one or more sub-blocks SBSA can be set in the array. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009123074(A) 申请公布日期 2009.06.04
申请号 JP20070298142 申请日期 2007.11.16
申请人 MEGA CHIPS CORP;KOBE UNIV 发明人 SAITO KAZUHIRO;YOSHIMOTO MASAHIKO;KAWAGUCHI HIROSHI;MIYAKOSHI JUNICHI;MURACHI YUICHIRO;HAMAMOTO MASANARI;IINUMA TAKAHIRO;ISHIHARA TOMOKAZU
分类号 G06T1/20;G06F9/38;G06F15/173;G06F15/80;H04N19/423;H04N19/436;H04N19/50;H04N19/51 主分类号 G06T1/20
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