| 摘要 |
An address decoder and a semiconductor memory device including the decoder are provided to simultaneously enable column selection signals in a parallel test mode, thereby reducing a read or write time for a parallel test. A pre-decoding unit(32) decodes addresses, and outputs plural pre-decoding address groups. The pre-decoding unit enables one pre-decoding address included in each pre-decoding address group in normal mode. The pre-decoding unit enables more than two pre-decoding addresses included in each pre-decoding address group in test mode. The test mode corresponds to a parallel test mode. The pre-decoding unit simultaneously enables the plural pre-decoding address groups in the parallel test mode. A main decoding unit(34) decodes the pre-decoding address groups.
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