| 摘要 |
In an information processing apparatus of this invention having a cache memory, a TLB and a TSB, a second retrieval unit (14) retrieves a second physical address from an address translation buffer (13) by using a second virtual address corresponding one-to-one to a first virtual address, and a prefetch controller (22) enters a first address translation pair of the first virtual address from an address translation table (11) into a cache memory (12) by using a second physical address which is a result of the retrieval, thereby largely shortening the processing time of a memory access when a TLB miss occurs at the time of the memory access. |
