发明名称 Latency tolerant distributed shared memory multiprocessor computer
摘要 A computer system having low memory access latency. In one embodiment, the computer system includes a network and one or more processing nodes connected via the network, wherein each processing node includes a plurality of processors and a shared memory connected to each of the processors. The shared memory includes a cache. Each processor includes a scalar processing unit, a vector processing unit and means for operating the scalar processing unit independently of the vector processing unit. Processors on one node can load data directly from and store data directly to shared memory on another processing node via the network.
申请公布号 US7543133(B1) 申请公布日期 2009.06.02
申请号 US20030643585 申请日期 2003.08.18
申请人 CRAY INC. 发明人 SCOTT STEVEN L.
分类号 G06F12/00 主分类号 G06F12/00
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