发明名称 |
Methods for reducing within chip device parameter variations |
摘要 |
A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.
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申请公布号 |
US7541613(B2) |
申请公布日期 |
2009.06.02 |
申请号 |
US20080117014 |
申请日期 |
2008.05.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ANDERSON BRENT ALAN;BUTT SHAHID AHMAD;GABOR ALLEN H.;LINDO PATRICK EDWARD;NOWAK EDWARD JOSEPH;RANKIN JED HICKORY |
分类号 |
H01L23/58;H01L21/00;H01L21/66 |
主分类号 |
H01L23/58 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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