发明名称 Processor purging system and method
摘要 A processor purging system comprising a translation lookaside buffer (TLB) having a plurality of translation pairs, at least one memory cache, and logic configured to detect whether at least one of the translation pairs corresponds to a purge signal. The logic is further configured to assert a purge detection signal indicative of whether at least one translation pair corresponds to the purge signal and to determine, based upon the purge detection signal, whether to search the memory cache for a translation pair corresponding to the purge signal.
申请公布号 US7543291(B2) 申请公布日期 2009.06.02
申请号 US20030632772 申请日期 2003.08.01
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 LESARTR GREGG BERNARD;STIRRETT DOUGLAS SHELBORN
分类号 G06F9/46;G06F9/26;G06F9/34;G06F12/10 主分类号 G06F9/46
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