发明名称 Cache memory system and method capable of adaptively accommodating various memory line sizes
摘要 A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.
申请公布号 US7543113(B2) 申请公布日期 2009.06.02
申请号 US20040883860 申请日期 2004.07.02
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 WALKER SHAWN;SOLTIS, JR. DONALD C.;BRUMMEL KARL
分类号 G06F12/00;G06F13/00;G06F13/28 主分类号 G06F12/00
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