发明名称 Error reduction for parallel, time-interleaved analog-to-digital converter
摘要 A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to frequency and multiplied by correction matrices to yield a corrected, reconstructed power spectrum for the PTIC. The technique is especially effective at removing gain and phase errors introduced by individual ADCs of the PTIC, including gain and phase errors that vary with frequency.
申请公布号 US7541958(B2) 申请公布日期 2009.06.02
申请号 US20060618792 申请日期 2006.12.30
申请人 TERADYNE, INC. 发明人 XU FANG
分类号 H03M1/12 主分类号 H03M1/12
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