发明名称 |
Semiconductor devices including test circuits and related methods of testing |
摘要 |
A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal. A latch may be coupled between the second transmission gate and an output of the semiconductor device, and the latch may be configured to latch a first logic value when a duration of the test clock signal pulse is less than a delay of the delay circuit and to latch a second logic value when a duration of the test clock signal pulse is greater than the delay of the delay circuit, and the first and second logic values be different. Related methods are also discussed.
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申请公布号 |
US7543201(B2) |
申请公布日期 |
2009.06.02 |
申请号 |
US20060463965 |
申请日期 |
2006.08.11 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM CHUL-SOO |
分类号 |
G01R31/28;G06F11/00;G06F13/42;H04L5/00 |
主分类号 |
G01R31/28 |
代理机构 |
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主权项 |
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地址 |
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