发明名称 STACK PACKAGE AND METHOD OF FABRICATING THE SAME
摘要 A stack package and a method for fabricating the same are provided to prevent the degradation of productivity of the whole stack package by omitting an additional patterning process for forming the rewiring by connecting a metal rewiring with a line width with a nano size between respective electrode terminals of the substrate and a pad for selecting each chip. A plurality of semiconductor chips(106,108,110,112) are stacked on a substrate(102) having an electrode terminal. Each semiconductor chip includes pads(106a,106b) for selecting a chip and a penetrating electrode is electrically connected by the penetrating electrode. One surface of the substrate including the semiconductor chip is sealed by an encapsulation material. The pads for selecting each chip of each stacked semiconductor chip is connected to the electrode terminal of the substrate by a metal rewiring(111) with a line width with a nano size formed along the edge of the semiconductor chip.
申请公布号 KR100900239(B1) 申请公布日期 2009.06.02
申请号 KR20080014582 申请日期 2008.02.18
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHOI, HYEONG SEOK;PARK, CHANG JUN;HAN, KWON WHAN;KIM, SEONG CHEOL;KIM, SUNG MIN;YANG, SEUNG TAEK;LEE, HA NA
分类号 H01L23/12;H01L23/28;H01L23/48 主分类号 H01L23/12
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