| 摘要 |
Typically, in designs for networking adapters, challenges are encountered where a partial word (e.g., 16 bit of IP checksum) has to be inserted into packets in buffers that are typically aligned to bus widths (e.g., 64 bit as in the case of 8x PCI Express interface). In fact, this is frequently required in hardware logic that implements a "checksum offload" feature. In many conventional designs, the hardware logic is required to insert the partial word into any given offset into the packet; this insert position in the buffers could be odd or even. Broadly contemplated herein, in accordance with at least one presently preferred embodiment of the present invention, is the implementation of a simple algorithm to store the 2 B IP checksum into any unaligned position within an 8 B word. This avoids the use of a logic-intensive implementation that employs 16 1:8 demultiplexers, or a latency-increasing approach of "read-modify-write".
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