ASYNCHRONOUS PIPELINE CONTROLLER

摘要

The present invention relates to an asynchronous control device (100 ) for controlling a stage of an asynchronous pipeline (10), the control device (100 ) comprising controllogic (104 ) and a non-transparent memoryelement (102 ),wherein the control logic (104 ) is adapted to receive a request signal (108), receive an acknowledgement signal (110), receive an output signal (112) from the non-transparent memory element, and generate an enable signal (114) forthe non-transparent memoryelement (102 ), wherein the non- transparent memoryelement (102 ) is adapted to receive one of the request signal (108) and the output signal from the non-transparent memory element (102) as an input signal, and receive the enable signal (114) generated by the control logic (104 ), thereby allowing for the input signalreceived by the non-transparent memoryelement (102 ) to be provided as the output signal from the non-transparent memoryelement (102 ). Byusing a non-transparent memoryelement in the control device it is possible to utilize standard cell technologies having inbuilt design-for-test technology, thus reducing the design-for-test overhead. Using less design-for-test overhead leads to a less expensive pipeline having less complex timing constraints.