| 摘要 |
Data synchronization is achieved in devices which transmit and/or receive audio and/or video data through the staged locking of phase locked loops (PLLs). According to an exemplary embodiment, a transmitter (15) includes a serial data source. An encoder (30) provides encoded data and includes a first PLL (34). A controller (20) includes a second PLL (24) which enables generation of a clock signal (WCLK). The controller (20) is coupled between the serial data source and the encoder (30) for providing the clock signal (WCLK) to the encoder (30). The first PLL (34) of the encoder (30) locks to the clock signal (WCLK). |
