发明名称 FAILURE ANALYSIS METHOD AND ITS DEVICE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technique of shortening a TAT of analysis and reducing a burden of an operator by making association of an access to a probing object and a coordinate on layout data easy, in failure analysis of a semiconductor device. SOLUTION: In confirmation of a probing position on an SEM image of real time, after carrying out coordinate system locking to correspond a coordinate system on an SEM image side and a coordinate system on a layout image side, the information specifying the probing position on a layout coordinate system side is displayed on the SEM image side, and, with it as a mark, the analysis system is configured so as to carry out the probing operation. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009117774(A) 申请公布日期 2009.05.28
申请号 JP20070292371 申请日期 2007.11.09
申请人 RENESAS TECHNOLOGY CORP 发明人 SHIMASE AKIRA;MIZUKOSHI KATSURO
分类号 H01L21/66;G01N23/225;H01J37/22 主分类号 H01L21/66
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