| 摘要 |
A design method of a semiconductor device comprising forming a base wafer by using a plurality of semiconductor chips including a plurality of functional macros, generating macro test information by testing the plurality of function macros of the plurality of semiconductor devices; and picking a macro that is prohibited from being used out of the plurality of function macros based on the macro test information and a net list of user circuit. Since tests are carried out at the phase of a base wafer, it is possible to improve yield rates in the manufacture of semiconductor integrated circuits.
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