发明名称 |
Cache memory system for a data processing apparatus |
摘要 |
A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.
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申请公布号 |
US2009138658(A1) |
申请公布日期 |
2009.05.28 |
申请号 |
US20080292148 |
申请日期 |
2008.11.12 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF MICHIGAN |
发明人 |
DRESLINSKI, JR. RONALD GEORGE;CHEN GREGORY KENGHO;MUDGE TREVOR NIGEL;BLAAUW DAVID THEODORE;SYLVESTER DENNIS |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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