发明名称 |
Correcting Offset Errors Associated With A Sub-ADC In Pipeline Analog To Digital Converters |
摘要 |
An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
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申请公布号 |
US2009135037(A1) |
申请公布日期 |
2009.05.28 |
申请号 |
US20070945278 |
申请日期 |
2007.11.27 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
AGARWAL NITIN;SINGH RAMESH KUMAR;PENTAKOTA VISVESVARAYA A.;JOHN DANTES;JOSHI SUPREET |
分类号 |
H03M3/00 |
主分类号 |
H03M3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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