发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS TEST METHOD
摘要 <p>When the operation frequency of a tester or an input/output circuit of a semiconductor integrated circuit device is lower than the frequency of a test input signal, an amount of disturbance allowance of a circuit under test can be measured without stopping the operation of the circuit under test included in the semiconductor integrated circuit device. The semiconductor integrated circuit device has a normal output signal counter for counting, when the circuit under test repeats, a plurality of times in sequence, a process for each input signal of an input signal group including one or two or more input signals, the number of how many times the circuit under test has outputted a normal output signal in response to a predetermined input signal among the input signal group.</p>
申请公布号 WO2009066764(A1) 申请公布日期 2009.05.28
申请号 WO2008JP71230 申请日期 2008.11.21
申请人 NEC CORPORATION;NOSE, KOICHI;MIZUNO, MASAYUKI 发明人 NOSE, KOICHI;MIZUNO, MASAYUKI
分类号 G01R31/30;G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/30
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