发明名称 MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS
摘要 Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers.
申请公布号 US2009138628(A1) 申请公布日期 2009.05.28
申请号 US20070945534 申请日期 2007.11.27
申请人 SPANSION LLC 发明人 KANADE RAVINDRA K.
分类号 G06F13/28 主分类号 G06F13/28
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