发明名称 Handling concurrent address translation cache misses and hits under those misses while maintaining command order
摘要 A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
申请公布号 US7539840(B2) 申请公布日期 2009.05.26
申请号 US20060420884 申请日期 2006.05.30
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 IRISH JOHN D.;MCBRIDE CHAD B.;OUDA IBRAHIM A.;WOTTRENG ANDREW H.
分类号 G06F12/00 主分类号 G06F12/00
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