发明名称 |
Sigma-delta modulation with minimized noise and fractional-N phase-locked loop including the same |
摘要 |
A sigma-delta modulator (SDM) includes a delay circuit and an operation circuit. The delay circuit generates multiple clock signals with different delays. The operation circuit includes a plurality of operation stages that operate with timing according to all of the clock signals for high-order sigma-delta modulation. Thus, noise may be dispersed for minimizing noise coupling. The SDM is used to particular advantage within a fractional-N phase-locked loop.
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申请公布号 |
US7538703(B2) |
申请公布日期 |
2009.05.26 |
申请号 |
US20070703260 |
申请日期 |
2007.02.07 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
YU HWA-YEAL |
分类号 |
H03M1/20 |
主分类号 |
H03M1/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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