发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To solve the problem that in a test using a scan test the activation ratio of the entire chip becomes very high instantaneously, thereby causing an unexpected voltage drop of a power source and making it impossible to obtain a correct test result. SOLUTION: For a scan chain group formed for each clock tree system within an LSI, a scan chain group structure which, without crossing a plurality of clock distribution areas obtained by dividing a clock supply area of one system clock tree, performs reconnection processing so that a connection distance becomes short in the distribution areas, a test clock input mechanism which makes an input test clock to each distribution area an independent sub clock phase, and an input clock on/off mechanism to each distribution area are achieved. A scan in/out and a scan test to be performed simultaneously are performed exclusively within one area or between areas, and all tests for each area and between areas are performed by a plurality of test steps. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009109192(A) 申请公布日期 2009.05.21
申请号 JP20070278308 申请日期 2007.10.26
申请人 HITACHI LTD 发明人 ITO YUICHI;FUJIMURA YASUHIRO;TSUTSUMIDA MITSUOKI;NAKAHARA SHIGERU
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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