发明名称 DATA PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a data processor having a parallel processing function which effectively eliminates a WAW (write after write) hazard even during out-of-order execution. SOLUTION: An arbitration circuit 1 outputs a time stamp information determination value TMD indicating the execution order of predicted execution write commands. An S buffer section 5 stores the time stamp information determination value of the write command executed most recently in a write area of the predicted execution write command, as a time stamp information value TMC for comparison. A time stamp comparing section 3 compares the time stamp information determination value TMD with the time stamp information value TMC for comparison. In the case of TMD>TMC, it is determined that the WAW hazard does not occur, and a control signal S3 permitting writing is output. In the case of TMD<TMC, it is determined that the WAW hazard occurs, and a control signal S3 prohibiting writing is output. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009110235(A) 申请公布日期 2009.05.21
申请号 JP20070281407 申请日期 2007.10.30
申请人 RENESAS TECHNOLOGY CORP 发明人 KUROSAWA TAKAYUKI
分类号 G06F9/38 主分类号 G06F9/38
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