| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase lock loop capable of widely dealing with dispersion in frequency characteristics of external clock signals and improving the stability of frequency characteristics without changing the central frequency. <P>SOLUTION: The phase lock loop comprises a phase comparison circuit 11 for receiving an external clock signal Si as a first input signal S1 and an output clock signal So or its divided signal as a second input signal S2 and outputting a phase difference detection signal Sd of a voltage corresponding to their phase difference, a loop filter 12 for outputting an oscillation control signal Sf of a voltage value corresponding to the phase difference from signal components in a predetermined band of the phase difference detection signal Sd, a voltage control oscillation circuit 13 for outputting an output clock signal So which oscillates at a frequency corresponding to the voltage value of the oscillation control signal Sf, and a lock state detection circuit 14 for detecting whether the second input signal S2 of the voltage control oscillation circuit 13 is locked or unlocked, wherein the loop filter 12 adjusts the lead-in range according to the lock detection result of the lock state detect circuit 14. <P>COPYRIGHT: (C)2009,JPO&INPIT |
