发明名称 |
ARITHMETIC PROCESSING UNIT, PROCESSOR, PROGRAM CONVERSION DEVICE, AND PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To provide an arithmetic processing unit which can guarantee a period for executing instructions in the shortest cycle when the arithmetic processing unit synchronizes with a hardware accelerator. SOLUTION: This processor simultaneously issues and executes instructions including instruction groups having concurrently executable instructions. The processor executes a program including a specific instruction. The specific instruction instructs to exclude an instruction subsequent to the specific instruction out of the instruction groups including the specific instruction, and to suspend issuing the instruction subsequent to the specific instruction only during a predetermined period immediately after the specific instruction is issued. COPYRIGHT: (C)2009,JPO&INPIT
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申请公布号 |
JP2009110209(A) |
申请公布日期 |
2009.05.21 |
申请号 |
JP20070281018 |
申请日期 |
2007.10.29 |
申请人 |
PANASONIC CORP |
发明人 |
KAKETA MASAHIDE;OZAKI SHINJI;YAMAMOTO TAKAO |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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