发明名称 TIMING GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide, by adding a small-scale circuit to a conventional configuration, a timing generating circuit enabling large calibration without affecting timing-setting range of a user. SOLUTION: A timing generating circuit, which generates, according to a reference clock and read data from a timing data storage to which rate signals and control signals for selecting timing data are input, timings for each rate, and which stores output data of an adder for adding calibration values of rising and falling edge to timing data set by a user, includes a skew adjustment unit, which in turn includes a delaying circuit for sending control signals and the rate signals. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009109359(A) 申请公布日期 2009.05.21
申请号 JP20070282390 申请日期 2007.10.30
申请人 YOKOGAWA ELECTRIC CORP 发明人 KUREBAYASHI SHINYA
分类号 G01R31/3183 主分类号 G01R31/3183
代理机构 代理人
主权项
地址