发明名称 SEMICONDUCTOR MEMORY, SYSTEM AND TEST SYSTEM
摘要 PROBLEM TO BE SOLVED: To eliminate a semiconductor memory having a memory cell which may be deteriorated in future. SOLUTION: In a memory cell, a pre-sense amplifier having capacitor accumulating electric charges in accordance with logic of data generates read-out voltage in accordance with electric charge amount read out from each memory cell in response to access request. A main sense amplifier amplifies the read-out voltage during activation of a sense amplifier activation signal. A timing generating circuit outputs a timing signal a predetermined time after receiving access request. A voltage detecting circuit outputs a detected signal when read-out voltage exceeds first voltage. A sense amplifier control circuit outputs the sense amplifier activation signal in synchronization with the detected signal or the timing signal. A mask circuit prohibits supply of the detected signal for the sense amplifier control circuit in order to output the sense amplifier activation signal in synchronization with the timing signal during a test mode. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009110623(A) 申请公布日期 2009.05.21
申请号 JP20070283973 申请日期 2007.10.31
申请人 FUJITSU MICROELECTRONICS LTD 发明人 NAKAZAWA MITSUHARU
分类号 G11C29/56;G11C11/22 主分类号 G11C29/56
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