发明名称 SYSTEM AND METHOD FOR TIME-TO-VOLTAGE CONVERSION WITH LOCK-OUT LOGIC
摘要 An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time.
申请公布号 US2009128216(A1) 申请公布日期 2009.05.21
申请号 US20080199020 申请日期 2008.08.27
申请人 RAO NARESH KESAVAN;YANOFF BRIAN DAVID;DU YANFENG;GUO JIANJUN 发明人 RAO NARESH KESAVAN;YANOFF BRIAN DAVID;DU YANFENG;GUO JIANJUN
分类号 G06G7/18 主分类号 G06G7/18
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