| 摘要 |
PROBLEM TO BE SOLVED: To provide a level shift circuit for preventing a high potential system latch circuit from being erroneously operated owing to an influence of parasitic capacitance existent between a drain and a substrate of a MOSFET of a low potential system. SOLUTION: In the present embodiment, disposition of capacitances (C) 51, 52 prevents erroneous operation of a latch circuit 100 by absorbing noise. That is, the capacitances (C) 51, 52 are connected between input terminals of an inverter (U1) 41 and an inverter (U2) 42 of the latch circuit 100 and a terminal (V2L) 6 that is a reference voltage of the latch circuit 100 that is a high potential system, so that any noise can be absorbed into the capacitances (C) 51, 52 to prevent erroneous operation of the latch circuit 100. COPYRIGHT: (C)2009,JPO&INPIT
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