发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which reduces a lead-out pattern region of wiring. <P>SOLUTION: The method includes steps of: performing exposure using a first photomask that has a pattern sequence where a hole pattern 12 enclosed by a light shielding portion or a translucent film and an auxiliary pattern 13 not to be transferred onto the semiconductor substrate are arranged at constant intervals, and the pitch between the hole pattern 12 and the auxiliary pattern 13 is a first pitch P<SB>hole</SB>calculated in terms of a dimension on the semiconductor substrate; and performing exposure by using a second photomask that has a pattern sequence where wiring patterns 9 enclosed by the light shielding portion or the translucent film are arranged at constant intervals, and the pitch between the wiring patterns 9 is a second pitch P<SB>line</SB>calculated in terms of a dimension on the semiconductor substrate. A value obtained by multiplying the second pitch P<SB>line</SB>by an integer m is equal to a value obtained by multiplying the first pitch P<SB>hole</SB>by an integer n, and the integer m is larger than the integer n. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009109581(A) 申请公布日期 2009.05.21
申请号 JP20070279343 申请日期 2007.10.26
申请人 TOSHIBA CORP 发明人 MASUKAWA KAZUYUKI;HASHIMOTO KOJI;KAWANO KENJI;KAI YASUNOBU
分类号 G03F1/36;G03F1/68 主分类号 G03F1/36
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