发明名称 Copy on access mechanisms for low latency data movement
摘要 In one embodiment, a data movement module (DMM) may receive a command to copy data from a source buffer to a destination buffer. One or more cache lines corresponding to addresses of the source buffer and the destination buffer may be invalidated. Also, an entry may be added to a queue to indicate that the command to copy is completion pending.
申请公布号 US7535918(B2) 申请公布日期 2009.05.19
申请号 US20050171602 申请日期 2005.06.30
申请人 INTEL CORPORATION 发明人 VASUDEVAN ANIL;BELL D. MICHAEL;SEN SUJOY;SARANGAM PARTHASARATHY
分类号 H04L12/56;H04J1/16 主分类号 H04L12/56
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