发明名称 |
Chip packaging process |
摘要 |
A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.
|
申请公布号 |
US7534653(B2) |
申请公布日期 |
2009.05.19 |
申请号 |
US20060563514 |
申请日期 |
2006.11.27 |
申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
HSUAN MIN-CHIH;HO KAI-KUANG;CHEN KUO-MING;TANG KUANG-HUI |
分类号 |
H01L21/00;H01L23/04;H01L23/31;H01L23/48;H01L23/485;H01L23/498;H01L23/552 |
主分类号 |
H01L21/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|