发明名称 Transmitter circuit, receiver circuit, clock data recovery phase locked loop circuit, data transfer method and data transfer system
摘要 [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.
申请公布号 US7535957(B2) 申请公布日期 2009.05.19
申请号 US20050104586 申请日期 2005.04.13
申请人 THINE ELECTRONICS, INC. 发明人 OZAWA SEIICHI;OKAMURA JUN-ICHI;ISHIZONE YOHEI;MIURA SATOSHI
分类号 H03K7/08;H03D3/18;H03K9/08;H03L7/087;H03L7/091;H03L7/113;H03M9/00;H04B14/04;H04L7/033;H04L25/45;H04L25/49;H04N11/04 主分类号 H03K7/08
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