发明名称 |
NROM memory cell, memory array, related devices and methods |
摘要 |
An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
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申请公布号 |
US7535048(B2) |
申请公布日期 |
2009.05.19 |
申请号 |
US20060346049 |
申请日期 |
2006.02.02 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
PRALL KIRK D.;FORBES LEONARD |
分类号 |
H01L21/8247;H01L27/108;G11C11/56;G11C16/04;H01L21/8246;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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