发明名称 |
Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) |
摘要 |
A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
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申请公布号 |
US7535272(B1) |
申请公布日期 |
2009.05.19 |
申请号 |
US20070944545 |
申请日期 |
2007.11.23 |
申请人 |
HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCHINSTITUTE CO. LTD. |
发明人 |
KWONG KWOK KUEN DAVID;WAN HO MING KAREN |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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地址 |
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