发明名称 Dynamic memory word line driver scheme
摘要 A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.
申请公布号 US7535749(B2) 申请公布日期 2009.05.19
申请号 US20060396306 申请日期 2006.03.30
申请人 MOSAID TECHNOLOGIES, INC. 发明人 LINES VALERIE L.
分类号 G11C11/24;G11C8/08;G11C11/408 主分类号 G11C11/24
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