发明名称 Reducing parasitic mutual capacitances
摘要 A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.
申请公布号 US7535080(B2) 申请公布日期 2009.05.19
申请号 US20050174246 申请日期 2005.06.30
申请人 INTEL CORPORATION 发明人 ZENG XIANG YIN;HE JIANGQI;XU BAOSHU
分类号 H01L29/93 主分类号 H01L29/93
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