| 摘要 |
The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q-1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q-1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B-C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.
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