| 摘要 |
A communication circuit comprises a plurality of receivers to receive the serial data from multiple lanes of a communication channel. The receivers may convert data received from the lanes from a serial to parallel format. Decoders may identify characters recovered from the different lanes, which collectively may define a word of width (i.e., character width) related to the number of lanes. Logic may determine when at least one of a start-of-frame and an end-of-frame character has been received. Parsing circuitry may then determine valid characters of a received word based on their placement relative to a start-of-frame character and/or an end-of-frame character. A controller may control when to present recovered data to at least one of storage registers or an output port, based on the character type identified by the decoder, its placement, an amount of characters parsed, and the number of characters already stored.
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