| 摘要 |
According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor, a first N-channel MOS transistor, a second inverter being composed of a second p-channel MOS transistor and a second N-channel transistor, a data-retaining portion having a third N-channel MOS transistor, a fourth N-channel MOS transistor, a fifth N-channel MOS transistor and a sixth N-channel MOS transistor, a data-reading portion for reading out data stored in the data-retaining portion via a first bit line, including at least one N-channel MOS transistor, wherein gate widths of the fifth N-channel MOS transistor and the sixth N-channel MOS transistor, respectively, is larger than gate widths of the first N-channel MOS transistor, the second N-channel MOS transistor, the third N-channel MOS transistor, the fourth N-channel MOS transistor, the first P-channel MOS transistor and the second P-channel MOS transistor, respectively.
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