发明名称 Interface test circuit
摘要 An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
申请公布号 US7535242(B2) 申请公布日期 2009.05.19
申请号 US20060417964 申请日期 2006.05.03
申请人 RAMBUS INC. 发明人 STOTT BRET;YEUNG PHILIP;BROOKS JOHN W.;LAU BENEDICT;TRAN CHANH V.;HO EUGENE C.
分类号 G01R31/26 主分类号 G01R31/26
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