| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that restrictions of data holding time are suppressed by a logic circuit between a signal for changing clock edge polarity of a latch circuit and the clock itself. SOLUTION: The latch circuit includes: a first terminal; a first data-gating circuit gating a second signal in response to a first signal to output a third signal; a second data-gating circuit reversely gating the second signal in response to the first signal with respect to the first data-gating circuit to output a fourth signal; a selector circuit outputting one of the third signal and the fourth signal in response to a fifth signal; and a bistable circuit storing a hold signal. COPYRIGHT: (C)2009,JPO&INPIT
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