| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a DLL circuit which reduces the risk of pulse loss even if a clock frequency is high. <P>SOLUTION: The DLL circuit 100 has a phase determination circuit 111 which compares phases of respective rising edges of CK and LCLK to generate a determination signal R-U/D, a phase determination circuit 112 which compares phases of falling edges of CK and LCLK to generate a determination signal F-U/D, a first adjustment circuit which adjusts the position of an LCLKR active edge based on the determination signal R-U/D, a second adjustment circuit which adjusts the position of an LCLKF active edge based on the determination signal F-U/D, a clock generation circuit which generates the LCLK based on the LCLKR and the LCLKF, a stop circuit 150 which stops adjustment operations of the second adjustment circuit responding to that an adjustment direction of the LCLKR active edge is reverse to that of the LCLKF active edge. <P>COPYRIGHT: (C)2009,JPO&INPIT |
