| 摘要 |
PROBLEM TO BE SOLVED: To easily wire signal lines of a semiconductor device by decreasing the number of wiring tracks used to wire the signal lines. SOLUTION: The signal line arrangement method includes: generating a clock tree and then dividing an LSI chip into a plurality of regions each including a clock buffer and a leaf cell (S15 in Fig. 1); moving clock buffers in the respective divided regions to a horizontal column where clock skew has a proper value (S16); and wiring output-side clock signal lines of the clock buffers disposed in the same horizontal column (S18). COPYRIGHT: (C)2009,JPO&INPIT
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