发明名称 DATA PROCESSING ARRANGEMENT, PIPELINE STAGE AND METHOD
摘要 <p>The asynchronous pipeline stage (20) comprises a data input (22) arranged for being coupled to a data providing environment (41) and a data output (24), arranged for being coupled to a data receiving environment (43). A controllable data retaining element (26) is coupled to the data input and the data output. The asynchronous pipeline stage further has a first handshake port (31) for exchanging handshake signals (ackN+1, reqiN) with the data providing environment and a second handshake port (32) for exchanging handshake signals (ackiv, reqN+1) with the data receiving environment. The pipeline stage (20) has a reset input (33) for receiving a reset signal (reset). The pipeline stage (20) assumes an initial state after receiving an asserted reset signal, and activates a handshake signal (reqN+1) at its second handshake port (32) after the reset signal has been de-asserted.</p>
申请公布号 WO2009060260(A1) 申请公布日期 2009.05.14
申请号 WO2007IB54496 申请日期 2007.11.06
申请人 KONINKLIJKE PHILIPS ELECTRONICS, N.V.;U.S. PHILIPS CORPORATION;PEETERS, ADRIANUS MARINUS GERARDUS;DE WIT, MARK 发明人 PEETERS, ADRIANUS MARINUS GERARDUS;DE WIT, MARK
分类号 G06F5/08 主分类号 G06F5/08
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