| 摘要 |
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during a scan based testing of an integrated circuit. In an embodiment, the encoder receives a test clock, including a capture pulse during a capture mode of the scan test, but forwards the capture pulse only to one of the clock domains and blocking the capture pulse to other clock domains. As a result, erroneous captures in the memory element receiving data from another clock domain is avoided without the need of closing timing on paths which are not functionally exercised.
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