| 摘要 |
PROBLEM TO BE SOLVED: To determine the delay time of a logical gate under the consideration of the influence of static and dynamic power supply voltage variation, that is, noises in a semiconductor integrated circuit such as digital LSI. SOLUTION: A timing analyzing apparatus for a semiconductor integrated circuit for analyzing the operation timing of a semiconductor integrated circuit equipped with a logic gate circuit including a plurality of logic gates, detects at least one of a power supply voltage and the ground potential of a power source, decomposes the noise waveform into frequency components, classifies the frequency components into low frequency components lower than a predetermined threshold frequency and high frequency components equal to or higher than the threshold frequency, calculates the static delay time of each of the logic gates due to the low frequency components, calculates the dynamic delay time of each of the logic gates due to the high frequency components, and determines the delay time of each of the logic gates by combining the calculated respective delay times. COPYRIGHT: (C)2009,JPO&INPIT
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